 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| - 1 - M471B1G73BH0 rev. 1.1, jul. 2011 samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" bas is, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, tradem ark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered tradem arks belong to their respective owners. ? 2011 samsung electronics co., ltd. all rights reserved. datasheet 204pin unbuffered sodimm based on 4gb b-die 78fbga with lead-free & halogen-free (rohs compliant)
- 2 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 revision history revision no. history draft date remark editor 1.0 - first spec release may. 2011 - j.y.lee 1.1 - changed timing parameters(setup/hold time) jul. 2011 - j.y.lee - 3 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 table of contents 204pin unbuffered sodimm based on 4gb b-die 1. ddr3 unbuffered sodimm ordering information .............. .............. .............. .............. .............. ........... ....................... 4 2. key features................................................................................................................ ................................................. 4 3. address configuration ....................................................................................................... ........................................... 4 4. x64 dimm pin configurations (front side/back side) .......................................................................... ......................... 5 5. pin description ............................................................................................................ ................................................. 6 6. input/output functional descrip tion............. .............. .............. .............. ............ ........... ........... ..................................... 7 7. function block diagram: ................................. .................................................................... .......................................... 8 7.1 8gb, 1gx64 module (populated as 2 ranks of x8 ddr3 sdrams) ................................................................. ...... 8 8. absolute maximum rati ngs .................................................................................................... ...................................... 9 8.1 absolute maximum dc ratings... ............................................................................................. ............................... 9 8.2 dram component operating temperature range ................................................................................. ............... 9 9. ac & dc operating conditions................................................................................................ ..................................... 9 9.1 recommended dc operating conditions (sstl-15)......... ..................................................................... ................ 9 10. ac & dc input measurement levels ........................................................................................... ............................... 10 10.1 ac & dc logic input levels for single-ended signals ....................................................................... ................... 10 10.2 v ref tolerances.................................................................................................................... ................................ 11 10.3 ac and dc logic input levels for differential sign als .............. .............. .............. .............. ............. ..................... 12 10.3.1. differential signals defini tion ........................................................................................ ................................. 12 10.3.2. differential swing requirement for clock (ck-ck ) and strobe (dqs-dqs ) ................................................ 12 10.3.3. single-ended requirements for differential signal s ............. .............. .............. .............. .............. ................. 13 10.3.4. differential input cross po int voltage ................................................................................. ........................... 14 10.4 slew rate definition for single ended input signal s ....................................................................... ...................... 14 10.5 slew rate definition for differ ential input signals ...... .............. .............. .............. .............. ......... ............................ 14 11. ac & dc output measurement levels .......................................................................................... ............................. 15 11.1 single ended ac and dc output levels...................................................................................... ......................... 15 11.2 differential ac and dc output levels ................ ...................................................................... ............................. 15 11.3 single-ended output slew rate .............. .............. .............. .............. .............. ........... ............ ............................... 15 11.4 differential output slew rate ............................................................................................. ................................... 16 12. dimm idd specification definition .......................................................................................... ..................................... 17 13. idd spec table ......... ............... .............. .............. .............. ........... ........... ........... .......... ............................................ 19 14. input/output capacitance ................................................................................................... ........................................ 20 15. electrical characteristics and ac timing .......... ......................................................................... .................................. 21 15.1 refresh parameters by device density...................................................................................... ........................... 21 15.2 speed bins and cl, trcd, trp, trc and tras for corre sponding bin ....... .............. .............. ............ ........... ...... 21 15.3 speed bins and cl, trcd, trp, trc and tras for corre sponding bin ........ .............. .............. ............ .......... ....... 21 15.3.1. speed bin table notes ...... ............................................................................................ ................................ 26 16. timing parameters by speed grade ..................... ...................................................................... ............................... 27 16.1 jitter notes .............................................................................................................. .............................................. 33 16.2 timing parameter notes............ ........................................................................................ .................................... 34 17. physical dimensions : ................................... ................................................................... ........................................... 35 17.1 512mx8 based 1gx64 module (2 ranks) - M471B1G73BH0 ........................................................................ ........ 35 - 4 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 1. ddr3 unbuffered sodimm ordering information note : 1. "##" - f8/h9/k0/ma 2. f8 - 1066mbps 7-7-7 / h9 - 1333mbps 9-9-9 / k0 - 1600mbps 11-11-11 / ma - 1866mbps 13-13-13 - ddr3-1866(13-13-13) is backward compatible to ddr3-1600(11-11-11), ddr3-1333(9-9-9), ddr3-1066(7-7-7) - ddr3-1600(11-11-11) is backward compatible to ddr3-1333(9-9-9), ddr3-1066(7-7-7) - ddr3-1333(9-9-9) is backward compatible to ddr3-1066(7-7-7) 2. key features ? jedec standard 1.5v 0.075v power supply ?v ddq = 1.5v 0.075v ? 400mhz f ck for 800mb/sec/pin, 533mhz f ck for 1066mb/sec/pin, 667mhz f ck for 1333mb/sec/pin, 800mhz f ck for 1600mb/sec/pin, 933mhz f ck for 1866mb/sec/pin ? 8 independent internal bank ? programmable cas latency: 5,6,7,8,9,10,11,13 ? programmable additive latency(posted cas ) : 0, cl - 2, or cl - 1 clock ? programmable cas write latency(cwl) = 5 (ddr3-800), 6 (ddr3-1066), 7 (ddr3-1333), 8 (ddr3-1600) and 9 (ddr3-1866) ? burst length: 8 (interleave without any limit, sequential with starting address ?000? only), 4 with tccd = 4 which does not al low seamless read or write [either on the fly using a12 or mrs] ? bi-directional differential data strobe ? on die termination using odt pin ? average refresh period 7.8us at lower then t case 85 c, 3.9us at 85 c < t case 95 c ? asynchronous reset 3. address configuration part number 2 density organization component composition number of rank height M471B1G73BH0-cf8/h9/k0/ma 8gb 1gx6 4 512mx8(k4b4g0846b-hc##)*16 2 30mm speed ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 unit 6-6-6 7-7-7 9-9-9 11-11-11 13-13-13 tck(min) 2.5 1.875 1.5 1.25 1.07 ns cas latency 6 7911 13 tck trcd(min) 15 13.125 13.5 13.75 13.91 ns trp(min) 15 13.125 13.5 13.75 13.91 ns tras(min) 37.5 37.5 36 35 34 ns trc(min) 52.5 50.625 49.5 48.75 47.91 ns organization row address column address bank address auto precharge 512mx8(4gb) based module a0-a15 a0-a9 ba0-ba2 a10/ap - 5 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 4. x64 dimm pin configurations (front side/back side) note : 1. nc = no connect, nu = not used, rfu = reserved future use 2. test(pin 125) is reserved for bus analysi s probes and is nc on normal memory modules. 3. this address might be connected to nc balls of the drams (depending on density); either way they will be connected to the te rmination resistor. samsung electronics co., ltd. reserves the right to change products and specifications without notice. pin front pin back pin front pin back pin front pin back 1 v refdq 2 v ss 71 v ss 72 v ss 139 v ss 140 dq38 3 v ss 4 dq4 key 141 dq34 142 dq39 5 dq0 6 dq5 73 cke0 74 cke1 143 dq35 144 v ss 7dq18 v ss 75 v dd 76 v dd 145 v ss 146 dq44 9 v ss 10 dqs 077 nc 78 a15 3 147 dq40 148 dq45 11 dm0 12dqs079 ba2 80 a14 3 149 dq41 150 v ss 13 v ss 14 v ss 81 v dd 82 v dd 151 v ss 152 dqs 5 15 dq2 16 dq6 83 a12/bc 84 a11 153 dm5 154 dqs5 17 dq3 18 dq7 85 a9 86 a7 155 v ss 156 v ss 19 v ss 20 v ss 87 v dd 88 v dd 157 dq42 158 dq46 21 dq8 22 dq12 89 a8 90 a6 159 dq43 160 dq47 23 dq9 24 dq13 91 a5 92 a4 161 v ss 162 v ss 25 v ss 26 v ss 93 v dd 94 v dd 163 dq48 164 dq52 27 dqs 1 28 dm1 95 a3 96 a2 165 dq49 166 dq53 29 dqs1 30 reset 97 a1 98 a0 167 v ss 168 v ss 31 v ss 32 v ss 99 v dd 100 v dd 169 dqs 6 170 dm6 33 dq10 34 dq14 101 ck0 102 ck1 171 dqs6 172 v ss 35 dq11 36 dq15 103 ck 0104ck 1 173 v ss 174 dq54 37 v ss 38 v ss 105 v dd 106 v dd 175 dq50 176 dq55 39 dq16 40 dq20 107 a10/ap 108 ba1 177 dq51 178 v ss 41 dq17 42 dq21 109 ba0 110 ras 179 v ss 180 dq60 43 v ss 44 v ss 111 v dd 112 v dd 181 dq56 182 dq61 45 dqs 246 dm2 113 we 114 s 0 183 dq57 184 v ss 47 dqs2 48 v ss 115 cas 116 odt0 185 v ss 186 dqs 7 49 v ss 50 dq22 117 v dd 118 v dd 187 dm7 188 dqs7 51 dq18 52 dq23 119 a13 3 120odt1189 v ss 190 v ss 53 dq19 54 v ss 121 s 1 122 nc 191 dq58 192 dq62 55 v ss 56 dq28 123 v dd 124 v dd 193 dq59 194 dq63 57 dq24 58 dq29 125 test 126 v refca 195 v ss 196 v ss 59 dq25 60 v ss 127 v ss 128 v ss 197 sa0 198 nc 61 v ss 62 dqs 3 129 dq32 130 dq36 199 v ddspd 200 sda 63 dm3 64 dqs3 131 dq33 132 dq37 201 sa1 202 scl 65 v ss 66 v ss 133 v ss 134 v ss 203 v tt 204 v tt 67 dq26 68 dq30 135 dqs 4136 dm4 69 dq27 70 dq31 137 dqs4 138 v ss - 6 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 5. pin description note: * the v dd and v ddq pins are tied common to a si ngle power-plane on these designs. pin name description number pin name description number ck0, ck1 clock inputs, positive line 2 dq0-dq63 data input/output 64 ck 0, ck 1 clock inputs, negative line 2 dm0-dm7 data masks/ data strobes, termination data strobes 8 cke0, cke1 clock enables 2 dqs0-dqs7 data strobes 8 ras row address strobe 1 dqs 0-dqs 7 data strobes complement 8 cas column address strobe 1 reset reset pin 1 we write enable 1 test logic analyzer specific test pin (no connect on sodimm) 1 s 0, s 1 chip selects 2 v dd core and i/o power 18 a0-a9, a11, a13-a15 address inputs 14 v ss ground 52 a10/ap address input/autoprecharge 1 v refdq v refca input/output reference 2 a12/bc address input/burst chop 1 v ddspd spd and temp sensor power 1 ba0-ba2 sdram bank addresses 3 v tt termination voltage 2 odt0, odt1 on-die termination control 2 nc reserved for future use 3 scl serial presence detect (spd) clock input 1 total 204 sda spd data input/output 1 sa0-sa1 spd address 2 - 7 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 6. input/output functional description symbol type function ck0-ck1 ck0 -ck1 input the system clock inputs. all address and command lines are sampled on the cross point of the rising edge of ck and falling edge of ck. a delay locked loop (dll) circuit is dr iven from the clock inputs an d output timing for read opera- tions is synchronized to the input clock. cke0-cke1 input activates the ddr3 sdram ck signal when high and deactiva tes the ck signal when low. by deactivating the clocks, cke low initiates the power down mode or the self refresh mode. s 0-s 1 input enables the associated ddr3 sdram command decoder w hen low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. rank 0 is selected by s 0; rank 1 is selected by s 1. r as , cas , we input when sampled at the cross point of the rising edge of ck and falling edge of ck , signals cas , r as , and we define the operation to be executed by the sdram. ba0-ba2 input selects which ddr3 sdram in ternal bank of eight is activated. odt0-odt1 input asserts on-die termination for dq, dm, dqs, and dqs signals if enabl ed via the ddr3 sdram mode register. a0-a9, a10/ap, a11 a12/bc a13-a15 input during a bank activate command cycle, defines the row addres s when sampled at the cross point of the rising edge of ck and falling edge of ck . during a read or write command cycle, defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or wr ite cycle. if ap is high, autoprecharge is selected and ba0- ban defines the bank to be precharged. if ap is low, au toprecharge is disabled. du ring a precharge command cycle, ap is used in conjunction with ba0-ban to control which bank(s) to precharge. if ap is high, all banks will be pre- charged regardless of the state of ba0-ban inputs. if ap is low, then ba0-ban are used to define which bank to pre- charge.a12(bc ) is sampled during read and write commands to determine if burst chop (on-the fly) will be performed (high, no burst chop; low, burst chopped) dq0-dq63 i/o data input/output pins. dm0-dm7 input the data write masks, associated with one data byte. in wr ite mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. dqs0-dqs7 dqs 0-dqs 7 i/o the data strobes, associated with one data byte, sourced with data transfers. in write mode, the data strobe is sourced by the controller and is centered in the data window. in read mode, the data strobe is sourced by the ddr3 sdrams and is sent at the leading edge of the data window. dqs signals are complements, and timing is relative to the crosspoint of respective dqs and dqs . v dd ,v ddspd, v ss supply power supplies for core, i/o, serial pr esence detect, temp sensor, and ground for the module. v refdq, v refca supply reference voltage for sstl15 inputs. sda i/o this is a bidirectional pin used to trans fer data into or out of the spd eeprom and temp sensor. a resistor must be connected from the sda bus line to v ddspd on the system planar to act as a pull up. scl input this signal is used to clock data into and out of the spd eeprom and temp sensor. sa0-sa1 input address pins used to select the seri al presence detect and temp sensor base address. test i/o the test pin is reserved for bus analysis tools and is not connected on normal memory modules reset input reset in active low this signal resets the ddr3 sdram - 8 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 7. function block diagram: 7.1 8gb, 1gx64 module (populated as 2 ranks of x8 ddr3 sdrams) s1 ras cas we ck1 ck1 cke1 odt1 a[0:n] /ba[0:n] s 0 ck0 ck0 cke0 odt0 dqs3 dqs 3 dm3 dqs dqs d11 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] dm 240 : r 1% dq[24:31] d3 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq 240 : r 1% vtt v dd vtt rank0 rank1 note : 1. dq wiring may differ from that shown how- ever ,dq, dm, dqs and dqs relationships are maintained as shown v ss v dd d0 - d15 v refca v ddspd spd ck0 v refdq d0 - d15 d0 - d15 d0 - d15, spd v tt ck1 ck 0 ck 1 reset v tt d8 - d15 d0 - d7 d0 - d7 d8 - d15 d0 - d7 dqs dqs dq[0:7] dm dqs1 dqs 1 dm1 dqs dqs d1 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] dm 240 : r 1% dq[8:15] d9 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq 240 : r 1% dqs dqs dq[0:7] dm dqs0 dqs 0 dm0 dqs dqs d0 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] dm 240 : r 1% dq[0:7] d8 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq 240 : r 1% dqs dqs dq[0:7] dm dqs2 dqs 2 dm2 dqs dqs d2 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] dm 240 : r 1% dq[16:23] d10 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq 240 : r 1% dqs dqs dq[0:7] dm dqs dqs d4 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] dm 240 : r 1% d12 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq 240 : r 1% dqs dqs dq[0:7] dm dqs dqs d14 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] dm 240 : r 1% d6 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq 240 : r 1% dqs dqs dq[0:7] dm dqs dqs d15 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] dm 240 : r 1% d7 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq 240 : r 1% dqs dqs dq[0:7] dm dqs dqs d13 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq dq[0:7] dm 240 : r 1% d5 cs ras cas we ck ck cke odt a[n:0]/ba[n:0] zq 240 : r 1% dqs dqs dq[0:7] dm dqs4 dqs 4 dm4 dq[32:39] dqs6 dqs 6 dm6 dq[48:55] dqs7 dqs 7 dm7 dq[56:63] dqs5 dqs 5 dm5 dq[40:47] v dd vtt a0 a1 a2 sa0 sa1 scl sda wp scl (spd) v7 v8 v5 v6 v2 v3 d6 d12 d3 d9 v tt address and controllines d7 d5 d10 d8 v1 v4 v9 v7 v6 v9 v8 v4 v3 d15 d13 d2 d0 d14 d4 d11 d1 v1 v2 v5 v1 - 9 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 8. absolute maximum ratings 8.1 absolute maximum dc ratings note : 1. stresses greater than those listed under ?absolute maximum rating s? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the ce nter/top side of the dram. for the measurement conditions, plea se refer to jesd51-2 standard. 3. v dd and v ddq must be within 300mv of each other at all times;and v ref must be not greater than 0.6 x v ddq , when v dd and v ddq are less than 500mv; v ref may be equal to or less than 300mv. 8.2 dram component oper ating temperature range note : 1. operating temperature t oper is the case surface temperature on the center/top side of t he dram. for measurement conditions, please refer to the jedec docu ment jesd51-2. 2. the normal temperature range specifies the temperatures where all dram specifications will be supported. during operation, t he dram case temperature must be main - tained between 0-85 c under all operating conditions 3. some applications require operation of the extended temperature range between 85 c and 95 c case temperature. full specifications are guaranteed in this range, but the following additional conditions apply: a) refresh commands must be doubled in frequency, ther efore reducing the refresh interval trefi to 3.9us. b) if self-refresh operation is required in the extended temperat ure range, then it is mandatory to either use the manual self- refresh mode with extended temperature range capability (mr2 a6 = 0b and mr2 a7 = 1b), in this case idd6 current can be increased around 10~20% than normal temperatur e range. 9. ac & dc operating conditions 9.1 recommended dc operating conditions (sstl-15) note : 1. under all conditions v ddq must be less than or equal to v dd . 2. v ddq tracks with v dd . ac parameters are measured with v dd and v ddq tied together. symbol parameter rating units note v dd voltage on v dd pin relative to v ss -0.4 v ~ 1.975 v v 1,3 v ddq voltage on v ddq pin relative to v ss -0.4 v ~ 1.975 v v 1,3 v in, v out voltage on any pin relative to v ss -0.4 v ~ 1.975 v v 1 t stg storage temperature -55 to +100 c 1, 2 symbol parameter rating unit note t oper operating temperature range 0 to 95 c 1, 2, 3 symbol parameter rating units note min. typ. max. v dd supply voltage 1.425 1.5 1.575 v 1,2 v ddq supply voltage for output 1.425 1.5 1.575 v 1,2 - 10 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 10. ac & dc input measurement levels 10.1 ac & dc logic input leve ls for single-ended signals [ table 1 ] single-ended ac & dc input levels for command and address note : 1. for input only pins except reset , v ref = v refca (dc) 2. see ?overshoot/undershoot specification? on page 18. 3. the ac peak noise on v ref may not allow v ref to deviate from v ref (dc) by more than 1% v dd (for reference : approx. 15mv) 4. for reference : approx. v dd /2 15mv 5. v ih (dc) is used as a simplified symbol for v ih.ca (dc100) 6. v il (dc) is used as a simplified symbol for v il.ca (dc100) 7. v ih (ac) is used as a simplified symbol for v ih.ca (ac175), v ih.ca (ac150), v ih.ca (ac135) and v ih.ca (ac125); v ih.ca (ac175) value is used when v ref + 175mv is referenced , v ih.ca (ac150) value is used when vr ef + 150mv is referenced, v ih.ca (ac135) value is used when vref + 135mv is referenced and v ih.ca (ac125) value is used when vref + 125mv is referenced. 8. v il (ac) is used as a simplified symbol for v il.ca (ac175) and v il.ca (ac150), v il.ca (ac135) and v il.ca (ac125); v il.ca (ac175) value is used when v ref - 175mv is refer- enced, v il.ca (ac150) value is used when v ref - 150mv is referenced, v il.ca (ac135) value is used when v ref - 135mv is referenced and v il.ca (ac125) value is used when v ref - 125mv is referenced. [ table 2 ] single-ended ac & dc input levels for dq and dm note : 1. for input only pins except reset , v ref = v refdq (dc) 2. see ?overshoot/undershoot specification? on page 18. 3. the ac peak noise on v ref may not allow v ref to deviate from v ref (dc) by more than 1% v dd (for reference : approx. 15mv) 4. for reference : approx. v dd /2 15mv 5. v ih (dc) is used as a simplified symbol for v ih.dq (dc100) 6. v il (dc) is used as a simplified symbol for v il.dq (dc100) 7. v ih (ac) is used as a simplified symbol for v ih.dq (ac175), v ih.dq (ac150) and v ih.dq (ac135) ; v ih.dq (ac175) value is used when v ref + 175mv is referenced, v ih.dq (ac150) value is used when v ref + 150mv is referenced. 8. v il (ac) is used as a simplified symbol for v il.dq (ac175), v il.dq (ac150) ; v il.dq (ac175) value is used when v ref - 175mv is referenced, v il.dq (ac150) value is used when v ref - 150mv is referenced. symbol parameter ddr3-800/1066/1333/1600 ddr3-1866 unit note min. max. min. max. v ih.ca (dc100) dc input logic high v ref + 100 v dd v ref + 100 v dd mv 1,5 v il.ca (dc100) dc input logic low v ss v ref - 100 v ss v ref - 100 mv 1,6 v ih.ca (ac175) ac input logic high v ref + 175 note 2 - - mv 1,2,7 v il.ca (ac175) ac input logic low note 2 v ref - 175 --mv1,2,8 v ih.ca (ac150) ac input logic high v ref +150 note 2 - - mv 1,2,7 v il.ca (ac150) ac input logic low note 2 v ref -150 --mv1,2,8 v ih.ca (ac135) ac input logic high - - v ref + 135 note 2 mv 1,2,7 v il.ca (ac135) ac input logic low - - note 2 v ref - 135 mv 1,2,8 v ih.ca (ac125) ac input logic high - - v ref +125 note 2 mv 1,2,7 v il.ca (ac125) ac input logic low - - note 2 v ref -125 mv 1,2,8 v refca (dc) reference voltage for add, cmd inputs 0.49*v dd 0.51*v dd 0.49*v dd 0.51*v dd v3,4 symbol parameter ddr3-800/1066 ddr3-1333/1600 ddr3-1866 unit note min. max. min. max. min. max. v ih.dq (dc100) dc input logic high v ref + 100 v dd v ref + 100 v dd v ref + 100 v dd mv 1,5 v il.dq (dc100) dc input logic low v ss v ref - 100 v ss v ref - 100 v ss v ref - 100 mv 1,6 v ih.dq (ac175) ac input logic high v ref + 175 note 2----mv1,2,7 v il.dq (ac175) ac input logic low note 2 v ref - 175 ----mv1,2,8 v ih.dq (ac150) ac input logic high v ref + 150 note 2 v ref + 150 note 2 - - mv 1,2,7 v il.dq (ac150) ac input logic low note 2 v ref - 150 note 2 v ref - 150 - - mv 1,2,8 v ih.dq (ac135) ac input logic high - - - - v ref + 135 note 2 mv 1,2,7 v il.dq (ac135) ac input logic low - - - - note 2 v ref - 135 mv 1,2,8 v ref dq (dc) reference voltage for dq, dm inputs 0.49*v dd 0.51*v dd 0.49*v dd 0.51*v dd 0.49*v dd 0.51*v dd v3,4 - 11 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 10.2 v ref tolerances. the dc-tolerance limits and ac-noise limits for the reference voltages v refca and v refdq are illustrate in figure 1. it shows a valid reference voltage v ref (t) as a function of time. (v ref stands for v refca and v refdq likewise). v ref (dc) is the linear average of v ref (t) over a very long period of time (e.g. 1 sec). this average has to meet the min/max requirements of v ref . fur- thermore v ref (t) may temporarily deviate from v ref (dc) by no more than 1% v dd . figure 1. illustration of vref(dc) tolerance and vref ac-noise limits the voltage levels for setup and hold time measurements v ih (ac), v ih (dc), v il (ac) and v il (dc) are dependent on v ref . "v ref " shall be understood as v ref (dc), as defined in figure 1. this clarifies, that dc-variations of v ref affect the absolute voltage a signal has to reach to achi eve a valid high or low level and therefore the time to which setup and hold is measured. system ti ming and voltage budgets need to account for v ref (dc) deviations from the optimum position within the data-eye of the input signals. this also clarifies that the dram setup/hold specification and derating values need to include time and voltage associated wit h v ref ac-noise. timing and voltage effects due to ac-noise on v ref up to the specified limit (+/-1% of v dd ) are included in dram timings and their associated deratings. voltage v dd v ss time - 12 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 10.3 ac and dc logic input levels for differential signals 10.3.1 differential signals definition figure 2. definition of differential ac-swing and "time above ac level" tdvac 10.3.2 differential swing requirement for clock (ck- ck ) and strobe (dqs- dqs ) note : 1. used to define a differential signal slew-rate. 2. for ck - ck use v ih /v il (ac) of add/cmd and v refca ; for dqs - dqs use v ih /v il (ac) of dqs and v refdq ; if a reduced ac-high or ac-low le vel is used for a signal group, then the reduced level applies also here. 3. these values are not defined, how ever they single-ended signals ck, ck , dqs, dqs need to be within the respective limits (v ih (dc) max, v il (dc)min) for single-ended sig- nals as well as the limitations for overshoot and undersh oot. refer to "overshoot and undershoot specification" [ table 3 ] allowed time before ringback (tdvac) for ck - ck and dqs - dqs . symbol parameter ddr3-800/1066/1333/1600/1866 unit note min max v ihdiff differential input high +0.2 note 3 v 1 v ildiff differential input low note 3 -0.2 v 1 v ihdiff (ac) differential input high ac 2 x (v ih (ac) - v ref ) note 3 v 2 v ildiff (ac) differential input low ac note 3 2 x (v il (ac) - v ref ) v2 slew rate [v/ns] tdvac [ps] @ |v ih/ldiff (ac)| = 350mv tdvac [ps] @ |v ih/ldiff (ac)| = 300mv tdvac [ps] @ |v ih/ldiff (ac)| = 270mv tdvac [ps] @ |v ih/ldiff (ac)| = 250mv min max min max min max min max > 4.0 75 - 175 - tbd - tbd - 4.0 57 - 170 - tbd - tbd - 3.0 50 - 167 - tbd - tbd - 2.0 38 - 163 - tbd - tbd - 1.8 34 - 162 - tbd - tbd - 1.6 29 - 161 - tbd - tbd - 1.4 22 - 159 - tbd - tbd - 1.2 13 - 155 - tbd - tbd - 1.0 0 - 150 - tbd - tbd - < 1.0 0 - 150 - tbd - tbd - 0.0 tdvac v ih .diff.min half cycle differential input voltage (i.e. dqs-dqs , ck-ck ) time tdvac v ih .diff.ac.min v il .diff.max v il .diff.ac.max - 13 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 10.3.3 single-ended requirements for differential signals each individual component of a differential signal (ck, dqs, ck , dqs ) has also to comply with cert ain requirements for single-ended signals. ck and ck have to approximately reach v seh min / v sel max (approximately equal to the ac-levels ( v ih (ac) / v il (ac) ) for add/cmd signals) in every half-cycle. dqs, dqs have to reach v seh min / v sel max (approximately the ac-levels ( v ih (ac) / v il (ac) ) for dq signals) in every half-cycle proceeding and follow- ing a valid transition. note that the applicable ac-levels for add/cmd and dq ?s might be different per speed-bin etc. e.g. if v ih 150(ac)/v il 150(ac) is used for add/cmd signals, then these ac-levels apply also for the single-ended signals ck and ck . figure 3. single-ended requirement for differential signals note that while add/cmd and dq signal requirements are with respect to v ref , the single-ended components of differential signals have a requirement with respect to v dd /2; this is nominally the same. the trans ition of single-ended signals through the ac-lev els is used to measure setup time. for single- ended components of differential signals the requirement to reach v sel max, v seh min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. [ table 4 ] single-ended levels for ck, dqs, ck , dqs note : 1. for ck, ck use v ih /v il (ac) of add/cmd; for strobes (dqs, dqs ) use v ih /v il (ac) of dqs. 2. v ih (ac)/v il (ac) for dqs is based on v refdq ; v ih (ac)/v il (ac) for add/cmd is based on v refca ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here 3. these values are not defined, however the single-ended signals ck, ck , dqs, dqs need to be within the respective limits (v ih (dc) max, v il (dc)min) for single-ended sig- nals as well as the limitations for overshoot and unders hoot. refer to "overshoot and undershoot specification" symbol parameter ddr3-800/1066/1333/1600/1866 unit note min max v seh single-ended high-level for strobes (v dd /2)+0.175 note3 v 1, 2 single-ended high-level for ck, ck (v dd /2)+0.175 note3 v 1, 2 v sel single-ended low-level for strobes note3 (v dd /2)-0.175 v1, 2 single-ended low-level for ck, ck note3 (v dd /2)-0.175 v1, 2 v dd or v ddq v seh min v dd /2 or v ddq /2 v sel max v seh v ss or v ssq v sel ck or dqs time - 14 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 10.3.4 differential input cross point voltage to guarantee tight setup and hold times as well as output skew para meters with respect to clock and strobe, each cross point vo ltage of differential input signals (ck, ck and dqs, dqs ) must meet the requirements in below table. the differential input cross point voltage v ix is measured from the actual cross point of true and complement signal to the mid level between of v dd and v ss . figure 4. v ix definition [ table 5 ] cross point voltage for differential input signals (ck, dqs) note : 1. extended range for v ix is only allowed for clock and if single-ended clock input signals ck and ck are monotonic, have a single-ended swing v sel / v seh of at least v dd /2 250 mv, and the differential slew rate of ck-ck is larger than 3 v/ ns. 2. the relation between v ix min/max and v sel /v seh should satisfy following. (v dd /2) + v ix (min) - v sel 25mv v seh - ((v dd /2) + v ix (max)) 25mv 10.4 slew rate definition for single ended input signals see "address / command setup, hold and derating" for si ngle-ended slew rate definitions for address and command signals. see "data setup, hold and slew rate derating" fo r single-ended slew rate definitions for data signals. 10.5 slew rate definition for differential input signals input slew rate for differential signals (ck, ck and dqs, dqs ) are defined and measured as shown in below. [ table 6 ] differential input slew rate definition note : the differential signal (i.e. ck - ck and dqs - dqs ) must be linear between these thresholds figure 5. differential input slew rate definition for dqs, dqs and ck, ck symbol parameter ddr3-800/1066/1333/1600/1866 unit note min max v ix differential input cross point voltage relative to v dd /2 for ck,ck -150 150 mv 2 -175 175 mv 1 v ix differential input cross point voltage relative to v dd /2 for dqs,dqs -150 150 mv 2 description measured defined by from to differential input slew rate for rising edge (ck-ck and dqs-dqs ) v ildiffmax v ihdiffmin v ihdiffmin - v ildiffmax delta trdiff differential input slew rate for falling edge (ck-ck and dqs-dqs ) v ihdiffmin v ildiffmax v ihdiffmin - v ildiffmax delta tfdiff v dd ck , dqs v dd /2 ck, dqs v ss v ix v ix v ix v ihdiffmin 0 v ildiffmax delta trdiff delta tfdiff - 15 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 11. ac & dc output measurement levels 11.1 single ended ac and dc output levels [ table 7 ] single ended ac and dc output levels note : 1. the swing of +/-0.1 x v ddq is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to v tt =v ddq /2. 11.2 differential ac and dc output levels [ table 8 ] differential ac and dc output levels note : 1. the swing of +/-0.2xv ddq is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to v tt =v ddq /2 at each of the differential outputs. 11.3 single-ended output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between v ol (ac) and v oh (ac) for single ended signals as shown in below. [ table 9 ] single ended output slew rate definition note : output slew rate is verified by design and charac terization, and may not be s ubject to production test. [ table 10 ] single ended output slew rate description : sr : slew rate q : query output (like in dq, which stands for data-in, query-output) se : single-ended signals for ron = rzq/7 setting note : 1) in two cased, a maximum slew rate of 6v/ns applies for a single dq signal within a byte lane. - case_1 is defined for a single dq signal within a byte lane whic h is switching into a certain direction (either from high to low of low to high) while all remaining dq signals in the same byte lane are static (i.e they stay at either high or low). - case_2 is defined for a single dq signals in the same byte la ne are switching into the opposite direction (i.e. from low to h igh or high to low respectively). for the remaining dq signal switching into the opposite direction, the regular maximum limit of 5 v/ns applies. figure 6. single-ended output slew rate definition symbol parameter ddr3-800/1066/1333/1600/1866 units note v oh (dc) dc output high measurement level (for iv curve linearity) 0.8 x v ddq v v om (dc) dc output mid measurement level (for iv curve linearity) 0.5 x v ddq v v ol (dc) dc output low measurement level (for iv curve linearity) 0.2 x v ddq v v oh (ac) ac output high measurement level (for output sr) v tt + 0.1 x v ddq v1 v ol (ac) ac output low measurement level (for output sr) v tt - 0.1 x v ddq v1 symbol parameter ddr3-800/1066/1333/1600/1866 units note v ohdiff (ac) ac differential output high measurement level (for output sr) +0.2 x v ddq v1 v oldiff (ac) ac differential output low measurement level (for output sr) -0.2 x v ddq v1 description measured defined by from to single ended output slew rate for rising edge v ol (ac) v oh (ac) v oh (ac)-v ol (ac) delta trse single ended output slew rate for falling edge v oh (ac) v ol (ac) v oh (ac)-v ol (ac) delta tfse parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 units min max min max min max min max min max single ended output slew rate srqse 2.5 5 2.5 5 2.5 5 2.5 5 2.5 5 1) v/ns v oh(ac) v ol(ac) delta trse delta tfse v tt - 16 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 11.4 differential output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between v oldiff (ac) and v oh- diff (ac) for differential signals as shown in below. [ table 11 ] differential output slew rate definition note : output slew rate is verified by design and charac terization, and may not be s ubject to production test. [ table 12 ] differential output slew rate description : sr : slew rate q : query output (like in dq, which stands for data-in, query-output) diff : differential signals for ron = rzq/7 setting figure 7. differential output slew rate definition description measured defined by from to differential output slew rate for rising edge v oldiff (ac) v ohdiff (ac) v ohdiff (ac)-v oldiff (ac) delta trdiff differential output slew rate for falling edge v ohdiff (ac) v oldiff (ac) v ohdiff (ac)-v oldiff (ac) delta tfdiff parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 units min max min max min max min max min max differential output slew rate srqdiff 5 10 5 10 5 10 5 10 5 12 v/ns v ohdiff (ac) v oldiff (ac) delta trdiff delta tfdiff v tt - 17 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 12. dimm idd specification definition symbol description idd0 operating one bank active-precharge current cke: high; external clock: on; tck, nrc, nras, cl: refer to component datasheet for detail pattern ; bl : 8 1) ; al : 0; cs : high between act and pre; command, address, bank address inputs: partially toggling ; data io: floating; dm: stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... ; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0; pattern details: refer to component datasheet for detail pat- tern idd1 operating one bank active-read-precharge current cke: high; external clock: on; tck, nrc, nras, nrcd, cl: refer to component datasheet for detail pattern ; bl : 8 1) ; al : 0; cs : high between act, rd and pre; command, address, bank address inputs, data io: partially toggling ; dm: stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... ; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0; pattern details: refer to component datasheet for detail pat- tern idd2n precharge standby current cke: high; external clock: on; tck, cl: refer to component datasheet for detail pattern ; bl: 8 1) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling ; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0; pattern details: refer to component datasheet for detail pattern idd2p0 precharge power-down current slow exit cke: low; external clock: on; tck, cl: refer to component datasheet for detail pattern ; bl: 8 1) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0; precharge power down mode: slow exit 3) idd2p1 precharge power-down current fast exit cke: low; external clock: on; tck, cl: refer to component datasheet for detail pattern ; bl: 8 1) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0; precharge power down mode: fast exit 3) idd2q precharge quiet standby current cke: high; external clock: on; tck, cl: refer to component datasheet for detail pattern ; bl: 8 1) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0 idd3n active standby current cke: high; external clock: on; tck, cl: refer to component datasheet for detail pattern ; bl: 8 1) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling ; data io: floating; dm: stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0; pattern details: refer to component datasheet for detail pattern idd3p active power-down current cke: low; external clock: on; tck, cl: refer to component datasheet for detail pattern ; bl: 8 1) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floating; dm :stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0 idd4r operating burst read current cke: high; external clock: on; tck, cl: refer to component datasheet for detail pattern ; bl: 8 1) ; al: 0; cs : high between rd; command, address, bank address inputs: partially toggling ; data io: seamless read data burst with different data between one burst and the next one ; dm: stable at 0; bank activity: all banks open, rd commands cycling through banks: 0,0,1,1,2,2,... ; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0; pattern details: refer to component datasheet for detail pattern idd4w operating burst write current cke: high; external clock: on; tck, cl: refer to component datasheet for detail pattern ; bl: 8 1) ; al: 0; cs : high between wr; command, address, bank address inputs: partially toggling ; data io: seamless write data burst with different data between one burst and the next one ; dm: stable at 0; bank activity: all banks open, wr commands cycling through banks: 0,0,1,1,2,2,... ; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at high ; pattern details: refer to component datasheet for detail pattern idd5b burst refresh current cke: high; external clock: on; tck, cl, nrfc: refer to component datasheet for detail pattern ; bl: 8 1) ; al: 0; cs : high between ref; command, address, bank address inputs: partially toggling ; data io: floating; dm: stable at 0; bank activity: ref command every nrfc ; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0; pattern details: refer to component datasheet for detail pattern idd6 self refresh current: normal temperature range tcase: 0 - 85c; auto self-refresh (asr): disabled 4) ; self-refresh temperature range (srt): n ormal 5) ; cke: low; external clock: off; ck and ck : low; cl: refer to component datasheet for detail pattern ; bl: 8 1) ; al: 0; cs , command, address, bank address, data io: floating; dm: stable at 0; bank activity: self-refresh operation; output buffer and rtt: enabled in mode registers 2) ; odt signal: floating idd6et self-refresh current: extended temperature range (optional) 6) tcase: 0 - 95c; auto self-refresh (asr): disabled 4) ; self-refresh temperature range (srt): extended 5) ; cke: low; external clock: off; ck and ck : low; cl: refer to component datasheet for detail pattern ; bl: 8 1) ; al: 0; cs , command, address, bank address, data io: floating; dm: stable at 0; bank activity: extended temperature self-refresh operation; output buffer and rtt: enabled in mode registers 2) ; odt signal: floating idd7 operating bank interleave read current cke: high; external clock: on; tck, nrc, nras, nrcd, nrrd, nfaw, cl: refer to component datasheet for detail pattern ; bl: 8 1) ; al: cl-1; cs : high between act and rda; command, address, bank address inputs: partially toggling ; data io: read data bursts with different data between one burst and the next one ; dm: stable at 0; bank activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0; pattern details: refer to component datasheet for detail pattern idd8 reset low current reset : low; external clock : off; ck and ck : low; cke : floating ; cs , command, address, bank address, data io : floating ; odt signal : floating - 18 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 note : 1) burst length: bl8 fixed by mrs: set mr0 a[1,0]=00b 2) output buffer enable: set mr1 a[12] = 0b; set mr1 a[5,1] = 01 b; rtt_nom enable: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b 3) precharge power down mode: set mr0 a12=0b for slow exit or mr0 a12=1b for fast exit 4) auto self-refresh (asr): set mr2 a6 = 0b to disable or 1b to enable feature 5) self-refresh temperature range (srt): set mr2 a7=0b for normal or 1b for extended temperature range 6) refer to dram supplier data sheet and/or dimm spd to determine if optional features or requirements are supported by ddr3 sd ram device 7) idd current measure method and detail patterns are described on ddr3 component datasheet 8) vdd and vddq are merged on module pcb. 9) dimm idd spec is measured with qoff condition (iddq values are not considered) - 19 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 13. idd spec table M471B1G73BH0 : 8gb (1gx64) module note : 1. dimm idd spec is calculated with consid ering de-actived rank(idle) is idd2n. symbol cf8 (ddr3-1066@cl=7) ch9 (ddr3-1333@cl=9) ck0 (ddr3-1600@cl=11) cma (ddr3-1866@cl=13) unit note idd0 480 480 520 tbd ma 1 idd1 560 560 600 tbd ma 1 idd2p0(slow exit) 240 240 240 tbd ma idd2p1(fast exit) 240 240 240 tbd ma idd2n 320 320 320 tbd ma idd2q 320 320 320 tbd ma idd3p 320 320 320 tbd ma idd3n 400 400 400 tbd ma idd4r 720 840 960 tbd ma 1 idd4w 760 880 1040 tbd ma 1 idd5b 1120 1320 1320 tbd ma 1 idd6 240 240 240 tbd ma idd7 1200 1520 1560 tbd ma 1 idd8 240 240 240 tbd ma - 20 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 14. input/output capacitance [ table 13 ] input/output capacitance note : this parameter is component input/output capacitance so that is different from module level capacitance. 1. although the dm, tdqs and tdqs pins have different functions, the loading matches dq and dqs 2. this parameter is not subject to production test. it is verified by design and characterization. the capacitance is measured according to jep147("procedure for me asuring input capacitance using a vector network analyzer( vna )") with v dd , v ddq , v ss , v ssq applied and all other pins floating (except the pin under test, cke, reset and odt as necessary). v dd =v ddq =1.5v, v bias =v dd /2 and on-die termination off. 3. this parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. absolute value of cck- cck 5. absolute value of cio(dqs)-cio( dqs ) 6. ci applies to odt, cs , cke, a0-a15, ba0-ba2, ras , cas , we . 7. cdi_ctrl applies to odt, cs and cke 8. cdi_ctrl=ci(ctrl)-0.5*(ci(clk)+ci( clk )) 9. cdi_add_cmd applies to a0-a15, ba0-ba2, ras , cas and we 10. cdi_add_cmd=ci(add_cmd) - 0.5*(ci(clk)+ci( clk )) 11. cdio=cio(dq,dm) - 0.5*(cio(dqs)+cio( dqs )) 12. maximum external load capacitance on zq pin: 5pf parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 units note min max min max min max min max min max input/output capacitance (dq, dm, dqs, dqs , tdqs, tdqs ) cio 1.5 3.0 1.5 2.7 1.5 2.5 1.5 2.3 1.4 2.2 pf 1,2,3 input capacitance (ck and ck) cck 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 pf 2,3 input capacitance delta (ck and ck) cdck 0 0.15 0 0.15 0 0.15 0 0.15 0 0.15 pf 2,3,4 input capacitance (all other input-only pins) ci 0.75 1.5 0.75 1.5 0.75 1.3 0.75 1.3 0.75 1.2 pf 2,3,6 input capacitance delta (dqs and dqs) cddqs 0 0.2 0 0.2 0 0.15 0 0.15 0 0.15 pf 2,3,5 input capacitance delta (all control input-only pins) cdi_ctrl -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 -0.4 0.2 pf 2,3,7,8 input capacitance delta (all add and cmd input-only pins) cdi_add_cmd -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 -0.4 0.4 pf 2,3,9,10 input/output capacitance delta (dq, dm, dqs, dqs , tdqs, tdqs ) cdio -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pf 2,3,11 input/output capacitance of zq pin czq - 3 - 3 - 3 - 3 - 3 pf 2, 3, 12 - 21 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 15. electrical characteristics and ac timing (0 c - 23 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 [ table 16 ] ddr3-1333 speed bins speed ddr3-1333 units note cl-nrcd-nrp 9 -9 - 9 parameter symbol min max internal read command to first data taa 13.5 (13.125) 9 20 ns act to internal read or write delay time trcd 13.5 (13.125) 9 - ns pre command period trp 13.5 (13.125) 9 - ns act to act or ref command period trc 49.5 (49.125) 9 - ns act to pre command period tras 36 9*trefi ns cl = 5 cwl = 5 tck(avg) 3.0 3.3 ns 1,2,3,4,6,10,11 cwl = 6,7 tck(avg) reserved ns 4 cl = 6 cwl = 5 tck(avg) 2.5 3.3 ns 1,2,3,6 cwl = 6 tck(avg) reserved ns 1,2,3,4,6 cwl = 7 tck(avg) reserved ns 4 cl = 7 cwl = 5 tck(avg) reserved ns 4 cwl = 6 tck(avg) 1.875 <2.5 ns 1,2,3,4,6 cwl = 7 tck(avg) reserved ns 1,2,3,4 cl = 8 cwl = 5 tck(avg) reserved ns 4 cwl = 6 tck(avg) 1.875 <2.5 ns 1,2,3,6 cwl = 7 tck(avg) reserved ns 1,2,3,4 cl = 9 cwl = 5,6 tck(avg) reserved ns 4 cwl = 7 tck(avg) 1.5 <1.875 ns 1,2,3,4,9 cl = 10 cwl = 5,6 tck(avg) reserved ns 4 cwl = 7 tck(avg) reserved ns 1,2,3 supported cl settings 5,6,7,8,9 nck supported cwl settings 5,6,7 nck - 24 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 [ table 17 ] ddr3-1600 speed bins speed ddr3-1600 units note cl-nrcd-nrp 11-11-11 parameter symbol min max internal read command to first data taa 13.75 (13.125) 9 20 ns act to internal read or write delay time trcd 13.75 (13.125) 9 - ns pre command period trp 13.75 (13.125) 9 - ns act to act or ref command period trc 48.75 (48.125) 9 - ns act to pre command period tras 35 9*trefi ns cl = 5 cwl = 5 tck(avg) 3.0 3.3 ns 1,2,3,4,7,10,11 cwl = 6,7,8 tck(avg) reserved ns 4 cl = 6 cwl = 5 tck(avg) 2.5 3.3 ns 1,2,3,7 cwl = 6 tck(avg) reserved ns 1,2,3,4,7 cwl = 7, 8 tck(avg) reserved ns 4 cl = 7 cwl = 5 tck(avg) reserved ns 4 cwl = 6 tck(avg) 1.875 <2.5 ns 1,2,3,4,7 cwl = 7 tck(avg) reserved ns 1,2,3,4,7 cwl = 8 tck(avg) reserved ns 4 cl = 8 cwl = 5 tck(avg) reserved ns 4 cwl = 6 tck(avg) 1.875 <2.5 ns 1,2,3,7 cwl = 7 tck(avg) reserved ns 1,2,3,4,7 cwl = 8 tck(avg) reserved ns 1,2,3,4 cl = 9 cwl = 5,6 tck(avg) reserved ns 4 cwl = 7 tck(avg) 1.5 <1.875 ns 1,2,3,4,7 cwl = 8 tck(avg) reserved ns 1,2,3,4 cl = 10 cwl = 5,6 tck(avg) reserved ns 4 cwl = 7 tck(avg) 1.5 <1.875 ns 1,2,3,7 cwl = 8 tck(avg) reserved ns 1,2,3,4 cl = 11 cwl = 5,6,7 tck(avg) reserved ns 4 cwl = 8 tck(avg) 1.25 <1.5 ns 1,2,3,9 supported cl settings 5,6,7,8,9,10,11 nck supported cwl settings 5,6,7,8 nck - 25 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 [ table 18 ] ddr3-1866 speed bins speed ddr3-1866 units note cl-nrcd-nrp 13-13-13 parameter symbol min max internal read command to first data taa 13.91 (13.125) 12 20 ns act to internal read or write delay time trcd 13.91 (13.125) 12 - ns pre command period trp 13.91 (13.125) 12 - ns act to act or ref command period trc 47.91 (47.125) 12 - ns act to pre command period tras 34 9*trefi ns cl = 5 cwl = 5 tck(avg) 3.0 3.3 ns 1,2,3,4,8,10, 11 cwl = 6,7,8,9 tck(avg) reserved ns 4 cl = 6 cwl = 5 tck(avg) 2.5 3.3 ns 1,2,3,8 cwl = 6 tck(avg) reserved ns 1,2,3,4,8 cwl = 7,8,9 tck(avg) reserved ns 4 cl = 7 cwl = 5 tck(avg) reserved ns 4 cwl = 6 tck(avg) 1.875 2.5 ns 1,2,3,4,8 cwl = 7,8,9 tck(avg) reserved ns 4 cl = 8 cwl = 5 tck(avg) reserved ns 4 cwl = 6 tck(avg) 1.875 <2.5 ns 1,2,3,8 cwl = 7 tck(avg) reserved ns 1,2,3,4,8 cwl = 8,9 tck(avg) reserved ns 4 cl = 9 cwl = 5,6 tck(avg) reserved ns 4 cwl = 7 tck(avg) 1.5 1.875 ns 1,2,3,4,8 cwl = 8 tck(avg) reserved ns 4 cwl = 9 tck(avg) reserved ns 4 cl = 10 cwl = 5,6 tck(avg) reserved ns 4 cwl = 7 tck(avg) 1.5 <1.875 ns 1,2,3,8 cwl = 8 tck(avg) reserved ns 1,2,3,4,8 cl = 11 cwl = 5,6,7 tck(avg) reserved ns 4 cwl = 8 tck(avg) 1.25 1.5 ns 1,2,3,4,8 cwl = 9 tck(avg) reserved ns 1,2,3,4 cl = 12 cwl = 5,6,7,8 tck(avg) reserved ns 4 cwl = 9 tck(avg) reserved ns 1,2,3,4 cl = 13 cwl = 5,6,7,8 tck(avg) reserved ns 4 cwl = 9 tck(avg) 1.07 <1.25 ns 1,2,3,9 supported cl settings 5,6,7,8,9,10,11,13 nck supported cwl settings 5,6,7,8,9 nck - 26 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 15.3.1 speed bin table notes absolute specification (t oper ; v ddq = v dd = 1.5v +/- 0.075 v); note : 1. the cl setting and cwl setting result in tck(avg).min and tck(avg).max requirements. when making a selection of tck(avg), bo th need to be fulfilled: requirements from cl setting as well as requirements from cwl setting. 2. tck(avg).min limits: since cas latency is not purely analog - data and strobe output are synchronized by the dll - all possi ble intermediate frequencies may not be guar- anteed. an application should use the next smaller jedec standard tck(avg) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating cl [nck] = taa [ns] / tck(avg) [ns], rounding up to the next "supportedcl". 3. tck(avg).max limits: calculate tck(avg) = taa.max / cl selected and round the resulting tck(avg) down to the next valid spee d bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). this result is tck(avg) .max corresponding to cl selected. 4. "reserved" settings are not allowed. user must program a different value. 5. any ddr3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to production tests but verified by design/ characterization. 6. any ddr3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to production tests but verified by design/ characterization. 7. any ddr3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to production tests but verified by design/ characterization. 8. any ddr3-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to production tests but verified by design/ characterization. 9. for devices supporting optional downshift to cl=7 and cl=9, taa/trcd/trp min must be 13.125 ns or lower. spd settings must b e programmed to match. for example, ddr3-1333(cl9) devices supporting downshift to ddr3-1066(cl7) should program 13.125 ns in spd bytes for taamin (byte 16), trcdm in (byte 18), and trpmin (byte 20). ddr3-1600(cl11) devices supporting downshift to ddr3-1333(cl 9) or ddr3-1066(cl7) should program 13.125 ns in spd bytes for taamin (byte16), trcdmin (byte 18), and trpmin (byte 20). ddr3-1866(cl13) devices supporting downshift to ddr3-1600(cl11) or ddr3-1333(cl9) or ddr3-1066(cl7) should program 13.125 ns in spd bytes for taamin (byte16), trcdmin (byte 18), and trpmin (byte 20). ddr3-1600 devices supporting down binning to ddr3-1333 or ddr3-1066 should program 13.125ns in spd byte for taamin (byte 16), trcdmin (byte 18) and trpmin (byte 20). once trp (byte 20) is programmed to 13.125n s, trcmin (byte 21,23) also should be programmed accodingly. for example, 49.125ns, (trasmin + tr pmin = 36ns + 13.125ns) for ddr3-1333 and 48.125ns (trasmin + trpmi n = 35ns + 13.125ns) for ddr3- 1600. 10. ddr3 800 ac timing apply if dram operates at lower than 800 mt/s data rate. 11. for cl5 support dimm spd include cl5 on supportable cas latency(byte 14-bit1 set high). 12. for devices supporting optional down binning to cl=11, cl=9 and cl=7, taa/trcd/trpmin must be 13.125ns. spd setting must b e programed to match. for example, ddr3-1866 devices supporting down binning to ddr3-1600 or ddr3-1333 or 1066 should program 13.125ns in spd bytes for taamin(byt e16), trcdmin(byte18) and trpmin (byte20). once trp (byte20) is programmed to 13.125ns, trcmin (byte21,23) also should be programmed accordingly. for e xample, 47.125ns (trasmin + trp- min = 34ns + 13.125ns) - 27 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 16. timing parameters by speed grade [ table 19 ] timing parameters by speed bins for ddr3-800 to ddr3-1333 (cont.) speed ddr3-800 ddr3-1066 ddr3-1333 units note parameter symbol min max min max min max clock timing minimum clock cycle time (dll off mode) tck(dll_off) 8 - 8 - 8 - ns 6 average clock period tck(avg) see speed bins table ps clock period tck(abs) tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max ps average high pulse width tch(avg) 0.47 0.53 0.47 0.53 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 0.47 0.53 0.47 0.53 tck(avg) clock period jitter tjit(per) -100 100 -90 90 -80 80 ps clock period jitter during dll locking period tjit(per, lck) -90 90 -80 80 -70 70 ps cycle to cycle period jitter tjit(cc) 200 180 160 ps cycle to cycle period jitter during dll locking period tjit(cc, lck) 180 160 140 ps cumulative error across 2 cycles terr(2per) - 147 147 - 132 132 - 118 118 ps cumulative error across 3 cycles terr(3per) - 175 175 - 157 157 - 140 140 ps cumulative error across 4 cycles terr(4per) - 194 194 - 175 175 - 155 155 ps cumulative error across 5 cycles terr(5per) - 209 209 - 188 188 - 168 168 ps cumulative error across 6 cycles terr(6per) - 222 222 - 200 200 - 177 177 ps cumulative error across 7 cycles terr(7per) - 232 232 - 209 209 - 186 186 ps cumulative error across 8 cycles terr(8per) - 241 241 - 217 217 - 193 193 ps cumulative error across 9 cycles terr(9per) - 249 249 - 224 224 - 200 200 ps cumulative error across 10 cycles terr(10per) - 257 257 - 231 231 - 205 205 ps cumulative error across 11 cycles terr(11per) - 263 263 - 237 237 - 210 210 ps cumulative error across 12 cycles terr(12per) - 269 269 - 242 242 - 215 215 ps cumulative error across n = 13, 14 ... 49, 50 cycles terr(nper) terr(nper)min = (1 + 0.68ln(n))*tjit(per)min terr(nper)max = (1 = 0.68ln(n))*tjit(per)max ps 24 absolute clock high pulse width tch(abs) 0.43 - 0.43 - 0.43 - tck(avg) 25 absolute clock low pulse width tcl(abs) 0.43 - 0.43 - 0.43 - tck(avg) 26 data timing dqs,dqs to dq skew, per group, per access tdqsq - 200 - 150 - 125 ps 13 dq output hold time from dqs, dqs tqh 0.38 - 0.38 - 0.38 - tck(avg) 13, g dq low-impedance time from ck, ck tlz(dq) -800 400 -600 300 -500 250 ps 13,14, f dq high-impedance time from ck, ck thz(dq) - 400 - 300 - 250 ps 13,14, f data setup time to dqs, dqs referenced to v ih (ac)v il (ac) levels tds(base) ac175 75 - 25 - - - ps d, 17 tds(base) ac150 125 - 75 - 30 - ps d, 17 data hold time to dqs, dqs referenced to v ih (dc)v il (dc) levels tdh(base) dc100 150 - 100 - 65 - ps d, 17 dq and dm input pulse width for each input tdipw 600 - 490 - 400 - ps 28 data strobe timing dqs, dqs differential read preamble trpre 0.9 note 19 0.9 note 19 0.9 note 19 tck 13, 19, g dqs, dqs differential read postamble trpst 0.3 note 11 0.3 note 11 0.3 note 11 tck 11, 13, b dqs, dqs differential output high time tqsh 0.38 - 0.38 - 0.4 - tck(avg) 13, g dqs, dqs differential output low time tqsl 0.38 - 0.38 - 0.4 - tck(avg) 13, g dqs, dqs differential write preamble twpre 0.9 - 0.9 - 0.9 - tck dqs, dqs differential write postamble twpst 0.3 - 0.3 - 0.3 - tck dqs, dqs rising edge output access time from rising ck, ck tdqsck -400 400 -300 300 -255 255 ps 13,f dqs, dqs low-impedance time (referenced from rl-1) tlz(dqs) -800 400 -600 300 -500 250 ps 13,14,f dqs, dqs high-impedance time (referenced from rl+bl/2) thz(dqs) - 400 - 300 - 250 ps 12,13,14 dqs, dqs differential input low pulse width tdqsl 0.45 0.55 0.45 0.55 0.45 0.55 tck 29, 31 dqs, dqs differential input high pulse width tdqsh 0.45 0.55 0.45 0.55 0.45 0.55 tck 30, 31 dqs, dqs rising edge to ck, ck rising edge tdqss -0.25 0.25 -0.25 0.25 -0.25 0.25 tck(avg) c dqs,dqs falling edge setup time to ck, ck rising edge tdss 0.2 - 0.2 - 0.2 - tck(avg) c, 32 dqs,dqs falling edge hold time to ck, ck rising edge tdsh 0.2 - 0.2 - 0.2 - tck(avg) c, 32 - 28 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 [ table 19 ] timing parameters by speed bins for ddr3-800 to ddr3-1333 (cont.) speed ddr3-800 ddr3-1066 ddr3-1333 units note parameter symbol min max min max min max command and address timing dll locking time tdllk 512 - 512 - 512 - nck internal read command to precharge command delay trtp max (4nck,7.5ns) - max (4nck,7.5ns) - max (4nck,7.5ns) - e delay from start of internal write transaction to internal read com- mand twtr max (4nck,7.5ns) - max (4nck,7.5ns) - max (4nck,7.5ns) - e,18 write recovery time twr 15 - 15 - 15 - ns e mode register set command cycle time tmrd 4 - 4 - 4 - nck mode register set command update delay tmod max (12nck,15ns) - max (12nck,15ns) - max (12nck,15ns) - cas to cas command delay tccd 4 - 4 - 4 - nck auto precharge write recovery + precharge time tdal(min) wr + roundup (trp / tck(avg)) nck multi-purpose register recovery time tmprr 1 - 1 - 1 - nck 22 active to precharge command period tras see ?speed bins and cl, trcd, trp, trc and tras for corresponding bin? on page 42 ns e active to active command period for 1kb page size trrd max (4nck,10ns) - max (4nck,7.5ns) - max (4nck,6ns) - e active to active command period for 2kb page size trrd max (4nck,10ns) - max (4nck,10ns) - max (4nck,7.5ns) - e four activate window for 1kb page size tfaw 40 - 37.5 - 30 - ns e four activate window for 2kb page size tfaw 50 - 50 - 45 - ns e command and address setup time to ck, ck referenced to v ih (ac) / v il (ac) levels tis(base) ac175 200 - 125 - 65 - ps b,16 tis(base) ac150 200+150 - 125+150 - 65+125 - ps b,16,27 command and address hold time from ck, ck referenced to v ih (dc) / v il (dc) levels tih(base) dc100 275 - 200 - 140 - ps b,16 control & address input pulse width for each input tipw 900 - 780 - 620 - ps 28 calibration timing power-up and reset calibration time tzqiniti 512 - 512 - 512 - nck normal operation full calibration time tzqoper 256 - 256 - 256 - nck normal operation short calibration time tzqcs 64 - 64 - 64 - nck 23 reset timing exit reset from cke high to a valid command txpr max(5nck, trfc + 10ns) - max(5nck, trfc + 10ns) - max(5nck, trfc + 10ns) - self refresh timing exit self refresh to commands not requiring a locked dll txs max(5nck,trf c + 10ns) - max(5nck,trf c + 10ns) - max(5nck,trf c + 10ns) - exit self refresh to commands requiring a locked dll txsdll tdllk(min) - tdllk(min) - tdllk(min) - nck minimum cke low width for self refresh entry to exit timing tckesr tcke(min) + 1tck - tcke(min) + 1tck - tcke(min) + 1tck - valid clock requirement after self refresh entry (sre) or power- down entry (pde) tcksre max(5nck, 10ns) - max(5nck, 10ns) - max(5nck, 10ns) - valid clock requirement before self refresh exit (srx) or power- down exit (pdx) or reset exit tcksrx max(5nck, 10ns) - max(5nck, 10ns) - max(5nck, 10ns) - - 29 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 [ table 19 ] timing parameters by speed bins for ddr3-800 to ddr3-1333 speed ddr3-800 ddr3-1066 ddr3-1333 units note parameter symbol min max min max min max power down timing exit power down with dll on to any valid command;exit pre- charge power down with dll frozen to commands not requiring a locked dll txp max (3nck, 7.5ns) - max (3nck, 7.5ns) - max (3nck,6ns) - exit precharge power down with dll frozen to commands re- quiring a locked dll txpdll max (10nck, 24ns) - max (10nck, 24ns) - max (10nck, 24ns) - 2 cke minimum pulse width tcke max (3nck, 7.5ns) - max (3nck, 5.625ns) - max (3nck, 5.625ns) - command pass disable delay tcpded 1 - 1 - 1 - nck power down entry to exit timing tpd tcke(min) 9*trefi tcke(min) 9*trefi tcke(min) 9*trefi tck 15 timing of act command to power down entry tactpden 1 - 1 - 1 - nck 20 timing of pre command to power down entry tprpden 1 - 1 - 1 - nck 20 timing of rd/rda command to power down entry trdpden rl + 4 +1 - rl + 4 +1 - rl + 4 +1 - timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden wl + 4 +(twr/ tck(avg)) - wl + 4 +(twr/ tck(avg)) - wl + 4 +(twr/ tck(avg)) - nck 9 timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden wl+4+wr +1 - wl+4+wr+1 - wl+4+wr+1 - nck 10 timing of wr command to power down entry (bc4mrs) twrpden wl + 2 +(twr/ tck(avg)) - wl + 2 +(twr/ tck(avg)) - wl + 2 +(twr/ tck(avg)) - nck 9 timing of wra command to power down entry (bc4mrs) twrapden wl +2 +wr +1 - wl +2 +wr +1 - wl +2 +wr +1 - nck 10 timing of ref command to power down entry trefpden 1 - 1 - 1 - 20,21 timing of mrs command to power down entry tmrspden tmod(min) - tmod(min) - tmod(min) - odt timing odt high time without write command or with write command and bc4 odth4 4 - 4 - 4 - nck odt high time with write command and bl8 odth8 6 - 6 - 6 - nck asynchronous rtt turn-on delay (power-down with dll fro- zen) taonpd 2 8.5 2 8.5 2 8.5 ns asynchronous rtt turn-off delay (power-down with dll fro- zen) taofpd 2 8.5 2 8.5 2 8.5 ns rtt turn-on taon -400 400 -300 300 -250 250 ps 7,f rtt_nom and rtt_wr turn-off time from odtloff reference taof 0.3 0.7 0.3 0.7 0.3 0.7 tck(avg) 8,f rtt dynamic change skew tadc 0.3 0.7 0.3 0.7 0.3 0.7 tck(avg) f write leveling timing first dqs/dqs rising edge after write leveling mode is pro- grammed twlmrd 40 - 40 - 40 - tck 3 dqs/dqs delay after write leveling mode is programmed twldqsen 25 - 25 - 25 - tck 3 write leveling setup time from rising ck, ck crossing to rising dqs, dqs crossing twls 325 - 245 - 195 - ps write leveling hold time from rising dqs, dqs crossing to rising ck, ck crossing twlh 325 - 245 - 195 - ps write leveling output delay twlo 0 9 0 9 0 9 ns write leveling output error twloe 0 2 0 2 0 2 ns - 30 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 [ table 20 ] timing parameters by speed bins for ddr3-1600, ddr3-1866 (cont.) speed ddr3-1600 ddr3-1866 units note parameter symbol min max min max clock timing minimum clock cycle time (dll off mode) tck(dll_off) 8 - 8 - ns 6 average clock period tck(avg) see speed bins table ps clock period tck(abs) tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max ps average high pulse width tch(avg) 0.47 0.53 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 0.47 0.53 tck(avg) clock period jitter tjit(per) -70 70 -60 60 ps clock period jitter during dll locking period tjit(per, lck) -60 60 -50 50 ps cycle to cycle period jitter tjit(cc) 140 120 ps cycle to cycle period jitter during dll locking period tjit(cc, lck) 120 100 ps cumulative error across 2 cycles terr(2per) -103 103 -88 88 ps cumulative error across 3 cycles terr(3per) -122 122 -105 105 ps cumulative error across 4 cycles terr(4per) -136 136 -117 117 ps cumulative error across 5 cycles terr(5per) -147 147 -126 126 ps cumulative error across 6 cycles terr(6per) -155 155 -133 133 ps cumulative error across 7 cycles terr(7per) -163 163 -139 139 ps cumulative error across 8 cycles terr(8per) -169 169 -145 145 ps cumulative error across 9 cycles terr(9per) -175 175 -150 150 ps cumulative error across 10 cycles terr(10per) -180 180 -154 154 ps cumulative error across 11 cycles terr(11per) -184 184 -158 158 ps cumulative error across 12 cycles terr(12per) -188 188 -161 161 ps cumulative error across n = 13, 14 ... 49, 50 cycles terr(nper) terr(nper)min = (1 + 0.68ln(n))*tjit(per)min terr(nper)max = (1 = 0.68ln(n))*tjit(per)max ps 24 absolute clock high pulse width tch(abs) 0.43 - 0.43 - tck(avg) 25 absolute clock low pulse width tcl(abs) 0.43 - 0.43 - tck(avg) 26 data timing dqs,dqs to dq skew, per group, per access tdqsq - 100 - 85 ps 13 dq output hold time from dqs, dqs tqh 0.38 - 0.38 - tck(avg) 13, g dq low-impedance time from ck, ck tlz(dq) -450 225 -390 195 ps 13,14, f dq high-impedance time from ck, ck thz(dq) - 225 - 195 ps 13,14, f data setup time to dqs, dqs referenced to v ih (ac)v il (ac) lev- els tds(base) ac150 10 - - - ps d, 17 tds(base) ac135 - - 0 - ps d, 17 data hold time to dqs, dqs referenced to v ih (ac)v il (ac) levels tdh(base) dc100 45 - 20 - ps d, 17 dq and dm input pulse width for each input tdipw 360 - 320 - ps 28 data strobe timing dqs, dqs differential read preamble trpre 0.9 note 19 0.9 note 19 tck 13, 19, g dqs, dqs differential read postamble trpst 0.3 note 11 0.3 note 11 tck 11, 13, b dqs, dqs differential output high time tqsh 0.4 - 0.4 - tck(avg) 13, g dqs, dqs differential output low time tqsl 0.4 - 0.4 - tck(avg) 13, g dqs, dqs differential write preamble twpre 0.9 - 0.9 - tck dqs, dqs differential write postamble twpst 0.3 - 0.3 - tck dqs, dqs rising edge output access time from rising ck, ck tdqsck -225 225 -195 195 ps 13,f dqs, dqs low-impedance time (referenced from rl-1) tlz(dqs) -450 225 -390 195 ps 13,14,f dqs, dqs high-impedance time (referenced from rl+bl/2) thz(dqs) - 225 - 195 ps 12,13,14 dqs, dqs differential input low pulse width tdqsl 0.45 0.55 0.45 0.55 tck 29, 31 dqs, dqs differential input high pulse width tdqsh 0.45 0.55 0.45 0.55 tck 30, 31 dqs, dqs rising edge to ck, ck rising edge tdqss -0.27 0.27 -0.27 0.27 tck(avg) c dqs,dqs falling edge setup time to ck, ck rising edge tdss 0.9 note 19 0.18 - tck(avg) c, 32 dqs,dqs falling edge hold time to ck, ck rising edge tdsh 0.3 note 11 0.18 - tck(avg) c, 32 - 31 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 [ table 20 ] timing parameters by speed bins for ddr3-1600, ddr3-1866 (cont.) speed ddr3-1600 ddr3-1866 units note parameter symbol min max min max command and address timing dll locking time tdllk 512 - 512 - nck internal read command to precharge command delay trtp max (4nck,7.5ns) - max (4nck,7.5ns) - e delay from start of internal write transaction to internal read com- mand twtr max (4nck,7.5ns) - max (4nck,7.5ns) - e,18 write recovery time twr 15 - 15 - ns e mode register set command cycle time tmrd 4 - 4 - nck mode register set command update delay tmod max (12nck,15ns) - max (12nck,15ns) - cas# to cas# command delay tccd 4 - 4 - nck auto precharge write recovery + precharge time tdal(min) wr + roundup (trp / tck(avg)) nck multi-purpose register recovery time tmprr 1 - 1 - nck 22 active to precharge command period tras see ?speed bins and cl, trcd, trp, trc and tras for corresponding bin? on page 42 ns e active to active command period for 1kb page size trrd max (4nck,6ns) - max (4nck, 5ns) - e active to active command period for 2kb page size trrd max (4nck,7.5ns) - max (4nck, 6ns) - e four activate window for 1kb page size tfaw 30 - 27 - ns e four activate window for 2kb page size tfaw 40 - 35 - ns e command and address setup time to ck, ck referenced to v ih (ac) / v il (ac) levels tis(base) ac175 45 - - - ps b,16 tis(base) ac150 170 - - - ps b,16 tis(base) ac135 - - 65 - ps b,16 tis(base) ac125 - - 150 - ps b,16,27 command and address hold time from ck, ck referenced to v ih (ac) / v il (ac) levels tih(base) dc100 120 - 100 - ps b,16 control & address input pulse width for each input tipw 560 - 535 - ps 28 calibration timing power-up and reset calibration time tzqiniti 512 - max(512nck,640ns) - nck normal operation full calibration time tzqoper 256 - max(256nck,320ns) - nck normal operation short calibration time tzqcs 64 - max(64nck,80ns) - nck 23 reset timing exit reset from cke high to a valid command txpr max(5nck, trfc + 10ns) - max(5nck, trfc + 10ns) - self refresh timing exit self refresh to commands not requiring a locked dll txs max(5nck,trfc + 10ns) - max(5nck,trfc + 10ns) - exit self refresh to commands requiring a locked dll txsdll tdllk(min) - tdllk(min) - nck minimum cke low width for self refresh entry to exit timing tckesr tcke(min) + 1tck - tcke(min) + 1nck - valid clock requirement after self refresh entry (sre) or power- down entry (pde) tcksre max(5nck, 10ns) - max(5nck, 10ns) - valid clock requirement before self refresh exit (srx) or power- down exit (pdx) or reset exit tcksrx max(5nck, 10ns) - max(5nck, 10ns) - - 32 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 [ table 20 ] timing parameters by speed bins for ddr3-1600, ddr3-1866 speed ddr3-1600 ddr3-1866 units note parameter symbol min max min max power down timing exit power down with dll on to any valid command;exit pre- charge power down with dll frozen to commands not requiring a locked dll txp max (3nck,6ns) - max(3nck,6ns) - exit precharge power down with dll frozen to commands re- quiring a locked dll txpdll max (10nck, 24ns) - max(10nck,24ns) - 2 cke minimum pulse width tcke max (3nck,5ns) - max(3nck,5ns) - command pass disable delay tcpded 1 - 2 - nck power down entry to exit timing tpd tcke(min) 9*trefi tcke(min) 9*trefi tck 15 timing of act command to power down entry tactpden 1 - 1 - nck 20 timing of pre command to power down entry tprpden 1 - 1 - nck 20 timing of rd/rda command to power down entry trdpden rl + 4 +1 - rl + 4 +1 - timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden wl + 4 +(twr/ tck(avg)) - wl + 4 +(twr/ tck(avg)) - nck 9 timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden wl + 4 +wr +1 - wl + 4 +wr +1 - nck 10 timing of wr command to power down entry (bc4mrs) twrpden wl + 2 +(twr/ tck(avg)) - wl + 2 +(twr/ tck(avg)) - nck 9 timing of wra command to power down entry (bc4mrs) twrapden wl +2 +wr +1 - wl +2 +wr +1 - nck 10 timing of ref command to power down entry trefpden 1 - 1 - 20,21 timing of mrs command to power down entry tmrspden tmod(min) - tmod(min) - odt timing odt high time without write command or with write command and bc4 odth4 4 - 4 - nck odt high time with write command and bl8 odth8 6 - 6 - nck asynchronous rtt turn-on delay (power-down with dll fro- zen) taonpd 2 8.5 2 8.5 ns asynchronous rtt turn-off delay (power-down with dll fro- zen) taofpd 2 8.5 2 8.5 ns rtt turn-on taon -225 225 -195 195 ps 7,f rtt_nom and rtt_wr turn-off time from odtloff reference taof 0.3 0.7 0.3 0.7 tck(avg) 8,f rtt dynamic change skew tadc 0.3 0.7 0.3 0.7 tck(avg) f write leveling timing first dqs pulse rising edge after tdqss margining mode is pro- grammed twlmrd 40 - 40 - tck 3 dqs/dqs delay after tdqs margining mode is programmed twldqsen 25 - 25 - tck 3 write leveling setup time from rising ck, ck crossing to rising dqs, dqs crossing twls 165 - 140 - ps write leveling hold time from rising dqs, dqs crossing to rising ck, ck crossing twlh 165 - 140 - ps write leveling output delay twlo 0 7.5 0 7.5 ns write leveling output error twloe 0 2 0 2 ns - 33 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 16.1 jitter notes specific note a unit ?tck(avg)? represents the actual tck(avg) of the input cl ock under operation. unit ?nck? represents one clock cycle of the input clock, counting the actual clock edges .ex) tmrd = 4 [nck] means; if one mode register set command is registered at tm, another mode register set command may be registered at tm +4, even if (tm+4 - tm) is 4 x tck(avg) + terr(4per),min. specific note b these parameters are measured from a command/address signal (cke, cs , ras , cas , we , odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck/ck ) crossing. the spec values are not affect ed by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. t hat is, these parameters should be met whether clock jitter is present or not. specific note c these parameters are measured from a data strobe signal (dqs, dqs ) crossing to its respective clock signal (ck, ck ) crossing. the spec values are not affected by the amount of clock jitter appl ied (i.e. tjit(per), tjit(cc), etc.), as these are relative to the clock signal crossing. that is, thes e parameters should be met whether clock jitter is present or not. specific note d these parameters are measured from a data signal (dm, dq0, dq1, etc.) transition edge to its respective data strobe signal (dqs, dqs ) crossing. specific note e for these parameters, the ddr3 sdram device supports tnparam [nck] = ru{ tparam [ns] / tck(avg) [ns] }, which is in clock cycles, assuming all input cloc k jitter specifications are sati sfied. for example, the device will support tnrp = ru{trp / tck( avg)}, which is in clock cycles, if all input clock jitter specificat ions are met. this means: for ddr3-800 6-6-6, of which trp = 15ns , the device will support tnrp = ru{trp / tck(avg)} = 6, as long as the input clock jitter specifications are met, i.e. precharge com - mand at tm and active command at tm+6 is valid even if (tm+6 - tm) is less than 15ns due to input clock jitter. specific note f when the device is operated with input clock jitter, this parameter needs to be derated by the actual terr(mper),act of the inp ut clock, where 2 <= m <= 12. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr3-800 sdra m has terr(mper),act,min = - 172 ps and terr(mper),act,max = + 193 ps, then tdqsck,min(derated) = tdqsck,min - terr(mper ),act,max = - 400 ps - 193 ps = - 593 ps and tdqsck,max(der- ated) = tdqsck,max - terr(mper),act,min = 400 ps + 172 ps = + 572 ps. similarly, tlz(dq) for ddr3-800 derates to tlz(dq),min(derated) = - 800 ps - 193 ps = - 993 ps and tlz(dq),max(derated) = 400 ps + 172 ps = + 572 ps. (caution on the min/max usage!) note that terr(mper),act,min is the minimum measured value of terr(nper) where 2 <= n <= 12, and terr(mper),act,max is the maximum meas ured value of terr(nper) where 2 <= n <= 12. specific note g when the device is operated with i nput clock jitter, this parameter needs to be der ated by the actual tjit(per),act of the inpu t clock. (output deratings are relative to the sdram input cloc k.) for example, if the measur ed jitter into a ddr3-800 sdram has tck(avg),act = 2500 ps, tjit(per),act,min = - 72 ps and tjit( per),act,max = + 93 ps, then trpre,min(derated) = trpre,min + tjit(per),act,min = 0.9 x tck(avg),act + tjit(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. similarly, tqh,min(derated) = tqh,min + tjit(per),act,min = 0.38 x tck(av g),act + tjit(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (caution on the min/ max usage!) - 34 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 16.2 timing parameter notes 1. actual value dependant upon measurement level definitions which are tbd. 2. commands requiring a locked dll are: read (and rap) and synchronous odt commands. 3. the max values are system dependent. 4. wr as programmed in mode register 5. value must be rounded-up to next higher integer value 6. there is no maximum cycle time limit besides the need to satisfy the refresh interval, trefi. 7. for definition of rtt turn-on time taon see "device operation & timing diagram datasheet" 8. for definition of rtt turn-off time taof see "device operation & timing diagram datasheet". 9. twr is defined in ns, for calculation of twrpden it is necessary to round up twr / tck to the next integer. 10. wr in clock cycles as programmed in mr0 11. the maximum read postamble is bound by tdqsck(min) plus tqsh(min) on the left side and thz(dqs)max on the right side. see " device operation & timing diagram datasheet. 12. output timing deratings are relative to the sdram input clock. when the device is operated with input clock jitter, this pa rameter needs to be derated by tbd 13. value is only valid for ron34 14. single ended signal parameter. refer to chapter 8 and chapter 9 for definition and measurement method. 15. trefi depends on t oper 16. tis(base) and tih(base) values are for 1v/ns cmd/add single-ended slew rate and 2v/ns ck, ck differential slew rate, note for dq and dm signals, v ref (dc) = v ref dq(dc). for input only pins except reset , v ref (dc)=v ref ca(dc). see "address/command setup, hold and derating" on component datasheet. 17. tds(base) and tdh(base) values are for 1v/ns dq single-ended slew rate and 2v/ns dqs, dqs differential slew rate. note for dq and dm signals, v ref (dc)= v ref dq(dc). for input only pins except reset , v ref (dc)=v ref ca(dc). see "data setup, hold and slew rate derating" on component datasheet. 18. start of internal write transaction is defined as follows ; for bl8 (fixed by mrs and on-the-fly) : rising clock edge 4 clock cycles after wl. for bc4 (on-the-fly) : rising clock edge 4 clock cycles after wl for bc4 (fixed by mrs) : rising clock edge 2 clock cycles after wl 19. the maximum read preamble is bound by tlzdqs(min) on the left side and tdqsck(max) on the right side. see "device operation & timing diagram datasheet" 20. cke is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in pro gress, but power-down idd spec will not be applied until finishing those operations. 21. although cke is allowed to be registered low after a refresh command once trefpden(min) is satisfied, there are cases where additional time such as txpdll(min) is also required. see "device operation & timing diagram datasheet". 22. defined between end of mpr read burst and mrs which reloads mpr or disables mpr function. 23. one zqcs command can effectively correct a minimum of 0.5 % (zqcorrection) of ron and rtt impedance error within 64 nck for all speed bins assuming the maximum sensitivities specified in the ?output driver voltage and temperature sensitivity? and ?odt voltage and temperature sensitivity? tables. the appropriate interval between zqcs commands can be determined from these tables and other application specific parameters. one method for calculating the interval between zqcs commands, given the temperature (tdriftrate) and voltage (vdriftrate) drift rates that the sdram is sub- ject to in the application, is illustrated. the interval could be defined by the following formula: where tsens = max(drttdt, drondtm) and vsens = max(drttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5% / c, vsens = 0.15% / mv, tdriftrate = 1 c / sec and vdriftrate = 15 mv / sec, then the interval between zqcs commands is calcu- lated as: 24. n = from 13 cycles to 50 cycles. this row defines 38 parameters. 25. tch(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling ed ge. 26. tcl(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edg e. 27. the tis(base) ac150 specifications are adjusted from the tis(base) ac175 specification by adding an additional 125 ps for d dr3-800/1066 or 100ps for ddr3- 1333/1600 of derating to accommodate for the lower alternate threshold of 150mv and another 25ps to account for the earlier ref erence point [(175mv - 150 mv) / 1 v/ns]. 28. pulse width of a input signal is defined as the width between the first crossing of v ref (dc) and the consecutive crossing of v ref (dc) 29. tdqsl describes the instantaneous differential input low pulse width on dqs-dqs , as measured from one falling edge to the next consecutive rising edge. 30. tdqsh describes the instantaneous differential input high pulse width on dqs-dqs , as measured from one rising edge to the next consecutive falling edge. 31. tdqsh, act + tdqsl, act = 1 tck, act ; with txyz, act being the actual measured value of the respective timing parameter in the application. 32. tdsh, act + tdss, act = 1 tck, act ; with txyz, act being the actual measured value of the respective timing parameter in t he application. 33. the tis(base) ac125 specifications are adjusted from the tis(base) ac135 specification by adding an additional 75ps for ddr 3-1866 and 65ps for ddr3-2133 to accommodate for the lower alternate threshold of 125mv and another 10ps to account for the earlier reference point [(135mv - 125mv) / 1 v/ns]. zqcorrection (tsens x tdriftrate) + (vsens x vdriftrate) 0.5 (1.5 x 1) + (0.15 x 15) = 0.133 ~ ~ 128ms - 35 - unbuffered sodimm datasheet ddr3 sdram rev. 1.1 17. physical dimensions : 17.1 512mx8 based 1gx64 module (2 ranks) - M471B1G73BH0 the used device is 512m x8 ddr3 sdram, fbga. ddr3 sdram part no : k4b4g0846b - hc** * note : tolerances on all dimensions 0.15 unless otherwise specified. 0.25 max 2.55 detail b detail a 1.00 0.10 0.45 0.03 4.00 0.10 0.10 ab m c 2x 4.00 0.10 0.10 ab m c 2x 1.80 (optional holes) 0.60 units : millimeters 21.00 24.80 63.60 39.00 ab max 3.8 1.00 0.10 spd 1.65 6 30.00 0.15 20.00 67.60 0.10 ab m c |
Price & Availability of M471B1G73BH0
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |